SH7760 Datasheet, PDF (311/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit
Name Value R/W Description
11
A2W2 1
10
A2W1 1
9
A2W0 1
R/W Area 2 Wait Control
R/W
These bits specify the number of wait cycles to be
R/W
inserted for area 2. An external wait input is available for
SRAM and MPX interfaces and is not available for
synchronous DRAM interface.
• When SRAM interface is in use:
Inserted wait cycles
RDY pin
000: 0
Disabled
001: 1
Enabled
010: 2
Enabled
011: 3
Enabled
100: 6
Enabled
101: 9
Enabled
110: 12
Enabled
111: 15
Enabled
• When synchronous DRAM interface is in use*¹:
Synchronous DRAM CAS latency cycles
000:
001:
010:
011:
100:
101:
Setting prohibited
1*²
2*²
3*²
4*²
5*²
110: Setting prohibited
111: Setting prohibited
Rev. 1.0, 02/03, page 261 of 1294