SH7760 Datasheet, PDF (372/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

The synchronous DRAM mode register should be configured only once after power-on reset
and before synchronous DRAM access, and the setting should not be changed once it is made.
CKIO
TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
D31−D0
CKE
(High)
Figure 10.30(1) Synchronous DRAM Mode Write Timing (PALL)
Rev. 1.0, 02/03, page 322 of 1294