SH7760 Datasheet, PDF (681/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

18.5.2 Repetition when the Smart Card Interface is in Receiver Mode (T = 0)
Figure 18.8 shows repetition operations when the smart card interface is in receiver mode. (1) to
(5) in figure 18.8 correspond to items 1 to 5 described below.
1. If checking of the received parity bit detects an error, the PER bit in SISSR is automatically set
to 1. If the RIE bit in SISCR is set for enable, an SIMERI request is issued. The PER bit in
SISSR should be cleared to 0 before the sampling timing for the next parity bit.
2. The RDRF bit in SISSR is not set for frames in which a parity error occurs.
3. If checking of the received parity bit detects no error, the PER bit in SISSR is not set.
4. If checking of the received parity bit detects no error, it is assumed that reception was
completed normally, and the RDRF bit in SISSR is automatically set to 1. If the RIE bit in
SISCR is 1 and the EIO bit is 0, an SIMRXI request is generated.
5. If a normal frame is received, the pin is maintained in a high-impedance state at the timing for
transmission of error signals.
nth transfer frame
Repeat frame
n + 1th transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP DE
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP Ds D0 D1 D2 D3 D4
(5)
RDRF
PER
(2)
(4)
(1)
(3)
Figure 18.8 Repetition in the Smart Card Interface Receiver Mode
18.5.3 Repetition when the Smart Card Interface is in Transmitter Mode (T = 0)
Figure 18.9 shows repetition operations when the smart card interface is in transmitter mode. (1)
to (4) in figure 18.9 correspond to items 1 to 4 described below.
1. After completion of transmission of one frame, if an error signal is returned from the receiver,
the ERS bit in SISSR is set to 1. If the RIE bit in SISCR is set to enable, an SIMERI request is
issued. The ERS bit in SISSR should be cleared to 0 before the sampling timing for the next
parity bit.
2. In T = 0 mode, the TEND bit in SISSR is not set for a frame when an error signal indicating an
error is received.
3. If no error signal is returned from the receiver, the ERS bit in SISSR is not set.
4. If an error signal is not returned from the receiver, it is assumed that transmission of one frame,
including repetition, is completed, and the TEND bit in SISSR is set to 1. At this time, if the
TIE bit in SISCR is set to enable, a TEI interrupt request is issued.
Rev. 1.0,02/03, page 631 of 1294