SH7760 Datasheet, PDF (1154/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

1, the condition match flag (CMFA/CMFB) for the respective channel is set for the matched
condition but exception handling is not started.
The condition match flags (CMFA, CMFB) are set by a break condition match, but are not
automatically reset. Therefore, a memory store instruction should be used on BRCR to clear
the flags to 0. For details of the exact setting conditions for the condition match flags, see
section 31.3.6, Condition Match Flag Setting.
4. When sequential condition mode has been selected and the channel B condition is matched
after the channel A condition has been matched, a break is effected at the instruction at which
the channel B condition was matched. For details of the operation when the channel A
condition match and channel B condition match occur close together, see section 31.3.8,
Contiguous A and B Settings for Sequential Conditions. With sequential conditions, only the
channel B condition match flag is set. To clear the channel A match when the channel A
condition has been matched but the channel B condition has not yet been matched in sequential
condition mode, B'0 should be written to the SEQ bit in BRCR.
31.3.4 Instruction Access Cycle Break
1. When an instruction access/read/word setting is made in BBRA/BBRB, an instruction access
cycle can be used as a break condition. In this case, breaking before or after execution of the
relevant instruction can be selected with the PCBA/PCBB bit in BRCR. When an instruction
access cycle is used as a break condition, clear the LSB of BARA/BARB to 0. A break will not
be generated if this bit is set to 1.
2. When a pre-execution break is specified, the break is effected when it is confirmed that the
instruction is to be fetched and executed. Therefore, an overrun-fetched instruction (an
instruction that is fetched but not executed when a branch or exception occurs) cannot be used
in a break. However, if a TLB miss or TLB protection violation exception occurs at the time of
the fetch of an instruction subject to a break, the break exception handling is carried out first.
The instruction TLB exception handling is performed when the instruction is re-executed (see
section 8.2, Exception Types and Priorities). Also, since a delayed branch instruction and the
delay slot instruction are executed as a single instruction, if a pre-execution break is specified
for a delay slot instruction, the break will be effected before execution of the delayed branch
instruction. However, a pre-execution break cannot be specified for the delay slot instruction
for an RTE instruction.
3. With a post-execution break, the instruction set as a break condition is executed, then a break
interrupt is generated before the next instruction is executed. When a post-execution break is
set for a delayed branch instruction, the delay slot is executed and the break is effected before
execution of the instruction at the branch destination (when the branch is made) or the
instruction two instructions ahead of the branch instruction (when the branch is not made).
Rev. 1.0, 02/03, page 1104 of 1294