SH7760 Datasheet, PDF (814/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Mailbox 0 is a receive-only box but Mailboxes 1 to 31 can operate as both receive and transmit
boxes, depending on the MBC bits in the Message Control. The following diagram shows the
structure of a Mailbox in detail.
Address
Data bus
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access Field Name
Size
H'100 + N*32 0
STDID[10:0]
RTR IDE
EXTID
[17:16]
16 bits
H'102 + N*32
EXTID[15:0]
16 bits Control
H'104 + N*32
NMC ATX DART MBC[2:0] 0
CBE
DLC[3:0]
8/16 bits
H'106 + N*32
TimeStamp[15:0]
16 bits Time stamp
H'108 + N*32 MSG_DATA_0 (first Rx/Tx byte)
MSG_DATA_1
8/16 bits
H'10A + N*32
H'10C + N*32
MSG_DATA_2
MSG_DATA_4
MSG_DATA_3
MSG_DATA_5
8/16 bits
8/16 bits
Data
H'10E + N*32
MSG_DATA_6
MSG_DATA_7
8/16 bits
H'110 + N*32
H'112 + N*32
Local acceptance filter mask 0 (LAFM0)
Local acceptance filter mask 1 (LAFM1)
16 bits
16 bits
LAFM
Notes: 1. All bits shadowed in gray are reserved and the write value should always be 0. The read value is not guaranteed.
2. ATX and DART are not supported by mailbox 0, and the MBC setting of mailbox 0 is restricted.
Figure 22.3 Mailbox N Structure
Rev. 1.0, 02/03, page 764 of 1294