SH7760 Datasheet, PDF (323/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit
Name Value R/W Description
8
A6TED2 0
7
A6TED1 0
6
A6TED0 0
R/W Address-OE/WE Assertion Delay A6
R/W
These bits set the delay time from address output to
R/W
OE/WE assertion in the connected PCMCIA interface.
The setting of these bits is selected when the PCMCIA
interface access TC bit is 1.
Wait cycles to be inserted
000: 0
001: 1
010: 2
011: 3
100: 6
101: 9
110: 12
111: 15
5
A5TEH2 0
4
A5TEH1 0
3
A5TEH0 0
R/W OE/WE Negation-Address Delay A5
R/W
These bits set the address hold delay time after OE/WE
R/W
negation in the connected PCMCIA interface. PCMCIA
interface. The setting of these bits is selected when the
PCMCIA interface access TC bit is 0.
Wait cycles to be inserted
000: 0
001: 1
010: 2
011: 3
100: 6
101: 9
110: 12
111: 15
Rev. 1.0, 02/03, page 273 of 1294