SH7760 Datasheet, PDF (618/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

17.3.9 FIFO Control Register (SCFCR)
SCFCR performs data count resetting and trigger data number setting for transmit and receive
FIFO registers, and also contains a loopback test enable bit.
SCFCR can always be read from and written to by the CPU.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
RST
RG2*¹
RST
RG1*¹
RST
RG0*^{1 RTRG1 RTRG0}
TTRG1 TTRG0
MCE*¹ TFRST
RFRST
LOOP
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 11 —
Initial Value R/W
All 0
R
10
RSTRG2*¹ 0
9
RSTRG1*¹ 0
8
RSTRG0*¹ 0
R/W
R/W
R/W
7
RTRG1
0
R/W
6
RTRG0
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
SCIF_RTS Output Active Trigger
The SCIF_RTS signal becomes high when the
number of receive data stored in SCFRDR
exceeds the trigger number shown below.
000:127
001:1
010:16
011:32
100:64
101:96
110:108
111:120
Receive FIFO Data Number Trigger
These bits are used to set the number of receive
data bytes that sets the RDF flag in SCFSR.
The RDF flag is set when the number of receive
data bytes in SCFRDR is equal to or greater than
the trigger set number shown below.
00:1
01:16
10:64
11:96
Rev. 1.0, 02/03, page 568 of 1294