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| SH7760 Datasheet, PDF (1261/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine | |||
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CKIO
A25-A0
CSn
RD/WR
RD
T1
Tw
Twe
T2
tAD
tCSD
tRWD
tRSD
tRSD
tAD
tCSD
tRWD
tRSD
D31-D0
(read)
WEn
D31-D0
(write)
tWED1
tWEDF
tWDD
tWDD
tRDS
tRDH
tWEDF
tWDD
BS
RDY
DACKn
(SA: IO memory)
DACKn
(SA: IO memory)
DACKn
(DA)
tBSD
tBSD
tRDYS
tRDYH
tDACD
tRDYS
tDACD
tDACDF
tDACD
tRDYH
tDACD
tDACDF
tDACD
NOTES: IO : Dack device
SA : Single address DMA transfer
DA : Dual address DMA transfer
DACK set to active-high
Figure 33.19 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait)
Rev. 1.0, 02/03, page 1211 of 1294
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