SH7760 Datasheet, PDF (691/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

19.3.1 Slave Control Register (ICSCR)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
- SDBS SIE GCAE FNA
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W
Bit
Bit Name
31 to 4 
Initial Value R/W
All 0
R
3
SDBS
0
R/W
2
SIE
0
R/W
1
GCAE
0
R/W
Description
Reserved
These bits are always read as 0, and the write
value should always be 0.
Slave Data Buffer Select
This bit is used to select the data buffer. The data
buffer has two modes; the FIFO buffer mode and
the single buffer mode.
Clearing SDBS to 0 will select the FIFO buffer
mode. In the receive mode, while the RDF flag is 1
with the receive byte count stored in the FIFO
buffer equal to or greater than the byte count
specified by RTRG3 to RTRG0, SCL is held low.
Reading the receive data from the FIFO buffer will
clear the RDF flag to 0 and release SCL from low
level.
Setting SDBS to 1 will select the single buffer
mode.
SCL will be held low from the moment the receive
data register receives a data packet until SDR is
cleared to 0.
0: FIFO buffer mode
1: Single buffer mode
Slave Interface Enable
Ensure to set this bit to 1 to have the slave to
operate. If this bit is low, the slave interface is
reset.
Setting the MIE bit to 1 will set this bit to 1.
General Call Acknowledgement Enable
Ensure to set this bit to 1 when the master
requires the slave to acknowledge a transmission
of a general call address.
Rev. 1.0, 02/03, page 641 of 1294