SH7760 Datasheet, PDF (516/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 12.1 shows a block diagram of the CPG.
XTAL
EXTAL
MD8
CKIO
DCK
MD2
MD1
MD0
Oscillation circuits
Crystal
oscillator
PLL circuit 1
×6
×12
Frequency
divider 1
×1
×1/2
×1/3
×1/4
×1/6
×1/8
PLL circuit 2
×1
PLL circuit 3
×1
×1
×1/2
×1/3
Frequency
divider 2
CPG control unit
Clock frequency
control circuit
Standby control
circuit
×1
×1/2
×1/4
×1/8
Frequency
divider 3
FRQCR
DCKDR
MCKCR
Bus interface
STBCR
STBCR2
CPU clock
(Ick) cycle Icyc
Peripheral clock
(Pck) cycle Pcyc
Module clock
(Fck)
Bus clock
(Bck) cycle Bcyc
Peripheral bus
Legend:
FRQCR : Frequency control register
DCKDR : Clock division register
MCKCR : Module clock control register
STBCR : Standby control register
STBCR2 : Standby control register 2
Figure 12.1 Block Diagram of CPG
Each of the CPG blocks functions as described below.
(1) PLL Circuit 1
PLL circuit 1 has a function for multiplying the clock frequency from the EXTAL pin or
crystal oscillator by 6 or 12. Starting and stopping of this circuit is controlled by the setting
of the frequency control register.
(2) PLL Circuit 2
PLL circuit 2 coordinates the phases of the bus clock and the clock signal output from the
Rev. 1.0, 02/03, page 466 of 1294