SH7760 Datasheet, PDF (706/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
- RTRG3 RTRG2 RTRG1 RTRG0 TTRG1 TTRG0 RFRST TFRST
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 8 
Initial Value R/W
All 0
R
7
RTRG3
0
R/W
6
RTRG2
0
R/W
5
RTRG1
0
R/W
4
RTRG0
0
R/W
Description
Reserved.
These bits are always read as 0. The write value
should always be 0.
Receive FIFO Data Count Trigger
These bits specify the receive byte count to set
ICFSR.RDF. The RDF flag is set to 1 when the
receive byte count in ICRXD reaches the trigger
byte count set in these bits. The following settings
are available:
0000: 1
0001: 2
0010: 3
0011: 4
0100: 5
0101: 6
0110: 7
0111: 8
1000: 9
1001: 10
1010: 11
1011: 12
1100: 13
1101: 14
1110: 15
1111: 16
Rev. 1.0, 02/03, page 656 of 1294