SH7760 Datasheet, PDF (609/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
4
RE
0
R/W Receive Enable
Enables or disables the start of serial reception
by the SCIF.
Serial reception is started when a start bit is
detected in this state in asynchronous mode or a
synchronization clock is input while the RE bit is
set to 1.
It should be noted that clearing the RE bit to 0
does not affect the DR, ER, BRK, RDF, FER,
PER, and ORER flags, which retain their states.
Serial reception begins once the start bit is
detected in these states.
0: Reception disabled
1: Reception enabled*
Note*: SCSMR and SCFCR settings must be
made, the reception format decided, and
the receive FIFO reset, before the RE bit
is set to 1.
3
REIE
0
R/W Receive Error Interrupt Enable
Enables or disables generation of receive-error
interrupt (ERI) and break interrupt (BRI) requests.
The REIE bit setting is valid only when the RIE bit
is 0.
Receive-error interrupt (ERI) and break interrupt
(BRI) requests can be cleared by reading 1 from
the ER, BRK, or ORER flag, then clearing the flag
to 0, or by clearing the RIE and REIE bits to 0.
When REIE is set to 1, ERI and BRI interrupt
requests will be generated even if RIE is cleared
to 0. In DMAC transfer, this setting is made if the
interrupt controller is to be notified of ERI and BRI
interrupt requests.
0: Receive-error interrupt (ERI) and break
interrupt (BRI) requests disabled
1: Receive-error interrupt (ERI) and break
interrupt (BRI) requests enabled
2
—
0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
Rev. 1.0, 02/03, page 559 of 1294