SH7760 Datasheet, PDF (1342/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

F. Power-On and Power-Off Procedures
• Power-on
 Supply the internal power after supplying power to the I/O and CPG.
 Supply power to V_DDQ and V_DD-CPG simultaneously.
 At power-on, the RESET signal is low. Normally, supply power to the I/O and CPG before
(or at the same time as) entering the signal lines (RESET, MRESET, MD0 to MD8, and
external clock). If the signal lines are entered first, the LSI may be damaged.
 Input high level to MRESET in compliance with the voltage level of the I/O and CPG
power supply voltage.
• Power-off
 When turning off the power, there are no restrictions for the timing of RESET and
MRESET.
 Turn off the I/O and CPG power supply voltage after (or at the same time as) turning off
the internal power supply voltage.
However, note that the internal power supply voltage may exceed the I/O and CPG power
supply voltage by a maximum of 0.3 V only when the system is being turned off.
 The power supply level must be lowered in compliance with the I/O and CPG power
supply voltage.
• The ratings and procedures for power-on and power-off are given below.
V_DDQ = V_DD-CPG = 0 V
The LSI may be damaged if
−0.3 V < V_in < V_DDQ + 0.3 V
−0.3 V < V_DD, V_DD-PLL1/2/3 < V_DDQ + 0.3 V
are not satisfied when V_DDQ = V . _DD-CPG
2.0V
1.2V
GND
Power-on
V_DDQ
V , V _{DD DD-PLL1/2/3}
Power-off
t_on
t_off
0≤t_on<10ms
0≤t_off<10ms
Figure F.1 Power-On and Power-Off Procedures
Rev. 1.0, 02/03, page 1292 of 1294