SH7760 Datasheet, PDF (982/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
Initial
Value R/W Description
1
DTERIE 0
R/W Data Timeout Error Interrupt Enable
0: Disables data timeout error interrupt (disables DTERI
flag setting).
1: Enables data timeout error interrupt (enables DTERI
flag setting).
0
CTERIE 0
R/W Command Timeout Error Interrupt Enable
0: Disables command timeout error interrupt (disables
CTERI flag setting).
1: Enables command timeout error interrupt (enables
CTERI flag setting).
• INTCR2
Bit: 7
-
Initial value: 0
R/W: R
6
5
-
-
0
0
RR
4
3
-
-
0
0
RR
2
1
0
-
- FRDYIE
0
0
0
R R R/W
Bit
Bit Name
7 to 
1
Initial
Value
All 0
0
FRDYIE 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W FIFO Ready Interrupt Enable
0: Disables FIFO ready interrupt (disables flag setting).
1: Enables FIFO ready interrupt (enables flag setting).
26.3.13 Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2)
The INTSTR registers enable or disable MMCIF interrupts MMCI3 to MMCI0.
• INTSTR0
Bit: 7
6
5
4
3
2
1
0
FEI FFI DRPI DTI CRPI CMDI DBSYI ^-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R
Rev. 1.0, 02/03, page 932 of 1294