SH7760 Datasheet, PDF (1023/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 27.2 Register Configuration (2)
Register Name
Abbrev.
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
Manual Reset
by RESET
Pin/WDT/
Multiple
Exception
Sleep
Standby
by Sleep
by
Instruction
Software
/Deep
by
/Each
Sleep
Hardware Module
MFI index register
MFIIDX H’0000
H’0000
Retained
* Retained
MFI general status register
MFIGSR H’0000
H’0000
Retained
Retained
MFI status/control register
MFISCR H’0040/H’0050*³ H’0040/H’0050*³ Retained
Retained
MFI memory control register
MFIMCR H’0000
H’0000
Retained
Retained
MFI on-chip interrupt control register MFIIICR H’0000
H’0000
Retained
Retained
MFI external interrupt control register MFIEICR H’0000
H’0000
Retained
Retained
MFI address register
MFIADR H’0000
H’0000
Retained
Retained
MFI data register
MFIDATA H’0000
H’0000
Retained
Retained
MFRAM Undefined
Start
Undefined
Retained
Retained
MFRAM Undefined
End
Undefined
Retained
Retained
Notes: * After exiting hardware standby mode, this LSI enters the power-on reset state by the
RESET pin.
*1. The external device can write to this register only when the MFI-RS pin is driven high.
The on-chip CPU cannot write to this register.
*2. The external device can write to bit 6 only via the MFI. The on-chip CPU cannot write to
this bit. Perform a reading of MFISCR after changing this bit to check for malfunctions.
*3. 80-series interface: 0040; 68-series interface: 0050
*4. The external device can write to bits 7, 5, 3, and 0 only via the MFI. The on-chip CPU
cannot write to these bits.
*5. The external device can write to bits 10 to 2 only via the MFI. The on-chip CPU cannot
write to these bits.
Rev. 1.0, 02/03, page 973 of 1294