SH7760 Datasheet, PDF (666/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
Initial
Value R/W Description
0
0
R
Reserved
This bit is always read as 0. The write value should also
always be 0.
[Legend]etu: Elementary Time Unit
18.3.7 Receive Shift Register (SIRSR)
SIRSR is a register for reception of serial data.
The smart card interface receives serial data input from the SIM_D pin in order, from the LSB or
MSB, and sets it in SIRSR, converting it to parallel data. When reception of one byte of data is
completed, the data is automatically transferred to SIRDR. The CPU cannot directly read or write
SIRSR.
18.3.8 Receive Data Register (SIRDR)
SIRDR is an 8-bit read-only register that stores received serial data.
When reception of one byte of serial data is completed, the smart card interface transfers the
received serial data from SIRSR to SIRDR for storage, and completes the reception operation.
Thereafter, SIRSR can receive data. In this way, SIRSR and SIRDR constitute a double buffer,
enabling continuous reception of data. SIRDR cannot be written from the CPU.
Bit: 7
6
5
4
3
2
1
0
SIRD7 SIRD6 SIRD5 SIRD4 SIRD3 SIRD2 SIRD1 SIRD0
Initial value: 0
0
0
R/W: R
R
R
0
0
RR
0
0
0
R
R
R
Bit
7 to 0
Bit
Name
SIRD
7 to 0
Initial
Value
All 0
R/W Description
R
Receive Data
These bits store received serial data.
Rev. 1.0,02/03, page 616 of 1294