SH7760 Datasheet, PDF (673/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

18.4.2 Register Settings
Table 18.3 shows a map of the bits in the registers used by the smart card interface.
Set 0 or 1 to a bit if indicated as 0 or 1 in the following table. Set a bit without 0/1 indication
according to below instructions.
Table 18.3 Register Settings for the Smart Card Interface
Register
SISMR
SIBRR
SISCR
SITDR
SISSR
SIRDR
SISCMR
SISC2R
SIWAIT
SIGRD
SISMPL
Bit 7
0
0
TIE
TDRE
0
EIO
Bit
Bit 6 Bit 5 Bit 4 Bit 3
Bit 2 Bit 1
0
PE
O/E 0
0
0
0
0
0
0
BRR2 BRR1
RIE
TE
RE
WAIT_IE TEIE CKE1
SITD[7:0]
RDRF ORER ERS PER
TEND WAIT_ER
SIRD[7:0]
LCB PB
0
SDIR
SINV RST
0
0
0
0
0
0
SIWAIT[15:0] (16-bit register)
SIGRD[7:0]
SISCMPL[10:0] (16-bit register, but bits 15 to 11 are 0)
Bit 0
0
BRR0
CKE0
0
SMIF
0
(1) Serial mode register (SISMR) setting
When the IC card is set for the direct convention, the O/E bit is set to 0; for the inverse
convention, it is set to 1.
(2) Bit rate register (SIBRR) setting
Sets the bit rate. For the method of computing settings, refer to section 18.4.3, Clocks.
(3) Serial control register (SISCR) settings
The different interrupts can be enabled and disabled using the TIE, RIE, TEIE, and WAIT_IE
bits.
By setting either the TE or RE bit to 1, transmission or reception is selected.
The CKE1 and CKE0 bits are used to select the clock output state. For details, refer to section
18.4.3, Clocks.
Rev. 1.0,02/03, page 623 of 1294