SH7760 Datasheet, PDF (1102/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
VSY VSY VSY VSY _- VSY VSY VSY VSY VSY VSY VSY VSY VSY VSY VSY
NW3 NW2 NW1 NW0
NP10 NP9 NP8 NP7 NP6 NP5 NP4 NP3 NP2 NP1 NP0
Initial value: 0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
R/W: R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Bit Name Initial Value R/W Description
15
HSYNW3 0
14
HSYNW2 0
13
HSYNW1 0
12
HSYNW0 0
R/W Horizontal Sync Signal Width
R/W _{Sets the width of the horizontal sync signals (CL1 and}
R/W _{Hsync) (unit: character = 8 dots).}
R/W
Specify a value of (width of horizontal sync signal) −1.
Example: For a horizontal sync signal width of 8 dots.
HSYNW = (8 dots/8 dots/character) −1 = 0 =
H’0
11 to 8 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
HSYNP7 0
6
HSYNP6 1
5
HSYNP5 0
4
HSYNP4 1
3
HSYNP3 0
2
HSYNP2 0
1
HSYNP1 0
0
HSYNP0 0
R/W Horizontal Sync Signal Output Position
R/W _{Sets the output position of the horizontal sync signals}
R/W _{(unit: character = 8 dots).}
R/W
R/W ^{Specify a value of (position of horizontal sync signal}
R/W ^{output) −1.}
R/W _{Example: For a LCD module with a width of 640 pixels.}
R/W
HSYNP = [(640/8)+1] −1 = 80 = H’50
In this case, the horizontal sync signal is
active from the 648th through the 655th dot.
Note: The following conditions must be satisfied:
HTCN ≥ HSYNP+HSYNW+1
HSYNP ≥ HDCN+1
Rev. 1.0, 02/03, page 1052 of 1294