SH7760 Datasheet, PDF (1029/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit
Name Value R/W Description
4

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
3
RD*³ 0
R/W*¹ Read
Setting this bit to 1 reads the MFRAM data indicated by
MFIADR into MFIDATA.*²
• Setting the RD and LOCK bits simultaneously to 1
results in the continuous read mode, and enables
high-speed data transfer. The RD bit remains 1 until
the RD bit is next written to 0, or until the LOCK bit is
cleared to 0.
• If not setting the LOCK bit simultaneously to 1,
reading of MFRAM is performed only once. The RD
bit is automatically cleared to 0
2, 1

All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
AI/AD 0
R/W*¹ Address auto-increment/decrement
This bit is valid only when the LOCK bit is 1. Each time
an MFRAM read or write operation occurs, the value in
MFIADR is automatically changed by +4 or by -4.
0: Auto-increment (+4)
1: Auto-decrement (-4)
Notes: *1. The external device can write to this bit via the MFI. The on-chip CPU cannot write to
this bit.
*2. If the on-chip CPU and the external device via the MFI access MFRAM concurrently,
the access via the MFI is handled first.
*3. Do not set the WT and RD bits simultaneously to 1.
*4. Performs continuous writing to MFRAM in 32-bit units. Data with a length of less than
32 bits is not written to MFRAM.
Rev. 1.0, 02/03, page 979 of 1294