SH7760 Datasheet, PDF (325/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Similarly, to write H'0230 to the area 3 SDMR register, arbitrary data is written to address H'FF94
0000 (address "Y") + H'08C0 (value "X") (= H'FF94 08C0). As a result, H'0230 is written to the
SDMR register. The range of value "X" is H'0000 to H'0FFC.
The lower 16 bits of the address are set in the synchronous DRAM mode register. The burst length
is 4 and 8. Setting to SDMR writes into the following addresses in bytes.
Bus Width
32
32
Burst Length CAS Latency
4
1
2
3
8
1
2
3
Area 2
H'FF90 0048
H'FF90 0088
H'FF90 00C8
H'FF90 004C
H'FF90 008C
H'FF90 00CC
Area 3
H'FF94 0048
H'FF94 0088
H'FF94 00C8
H'FF94 004C
H'FF94 008C
H'FF94 00CC
For a 32-bit bus:
17 16 15 14 13 12 11 10 9 8
7
6
5
4
3
2
10
Address 0 0 0 0 0 0 0 0 0 LMODE2 LMODE1 LMODE0 WT BL2 BL1 BL0
LMODE:
BL:
WT:
←−→
10 bits set when bus width is 32 bits
RAS-CAS latency
Burst length
Wrap type (0: Sequential)
BL
000: Setting prohibited
001: Setting prohibited
010: 4
011: 8
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
LMODE
000: Setting prohibited
001: 1
010: 2
011: 3
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Rev. 1.0, 02/03, page 275 of 1294