SH7760 Datasheet, PDF (1161/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

31.6 Examples of Use
(1) Instruction Access Cycle Break Condition Settings
1. Register settings: BASRA = H'80 / BARA = H'0000 0404 / BAMRA = H'00 /
BBRA = H'0014 / BASRB = H'70 / BARB = H'0000 8010 / BAMRB = H'01 /
BBRB = H'0014 / BDRB = H'0000 0000 / BDMRB = H'0000 0000 / BRCR = H'0400
• Conditions set: Independent channel A/channel B mode
 Channel A: ASID: H'80 / address: H'0000 0404 / address mask: H'00
Bus cycle: instruction access (post-instruction-execution), read (operand size not
included in conditions)
 Channel B: ASID: H'70 / address: H'0000 8010 / address mask: H'01
Data: H'0000 0000 / data mask: H'0000 0000
Bus cycle: instruction access (pre-instruction-execution), read (operand size not
included in conditions)
A user break is generated after execution of the instruction at address H'0000 0404 with ASID
= H'80, or before execution of an instruction at addresses H'0000 8000 to H'0000 83FE with
ASID = H'70.
2. Register settings: BASRA = H'80 / BARA = H'0003 7226 / BAMRA = H'00 /
BBRA = H'0016 / BASRB = H'70 / BARB = H'0003 722E / BAMRB = H'00 /
BBRB = H'0016 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0008
• Conditions set: Channel A → channel B sequential mode
 Channel A: ASID: H'80 / address: H'0003 7226 / address mask: H'00
Bus cycle: instruction access (pre-instruction-execution), read, word
 Channel B: ASID: H'70 / address: H'0003 722E / address mask: H'00
Data: H'0000 0000 / data mask: H'0000 0000
Bus cycle: instruction access (pre-instruction-execution), read, word
The instruction at address H'0003 7266 with ASID = H'80 is executed, then a user break is
generated before execution of the instruction at address H'0003 722E with ASID = H'70.
3. Register settings: BASRA = H'80 / BARA = H'0002 7128 / BAMRA = H'00 /
BBRA = H'001A / BASRB = H'70 / BARB = H'0003 1415 / BAMRB = H'00 /
BBRB = H'0014 / BDRB = H'0000 0000 / BDMRB = H'0000 0000 / BRCR = H'0000
• Conditions set: Independent channel A/channel B mode
 Channel A: ASID: H'80 / address: H'0002 7128 / address mask: H'00
Bus cycle: CPU, instruction access (pre-instruction-execution), write, word
Rev. 1.0, 02/03, page 1111 of 1294