SH7760 Datasheet, PDF (926/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
12

11
DACKP0
10
DACKD0
9
DACKP1
8
DACKD1
7
DRAKP0
6
DRAKD0
5
DRAKP1
4
DRAKD1
3 to 1 
0
BRGRST
Initial value R/W Description
0
R
Reserved
This bit is always read as 0, and the write value
should always be 0.
0
R/W Controls the pin state for DACK0 in software
1
R/W standby mode.
00: Hi-Z state
01: Output
10: Hi-Z state with pull-up on
11: Setting prohibited
0
R/W Controls the pin state for DACK1 in software
1
R/W standby mode.
00: Hi-Z state
01: Output
10: Hi-Z state with pull-up on
11: Setting prohibited
0
R/W Controls the pin state for DRAK0 in software
1
R/W standby mode.
00: Hi-Z state
01: Output
10: Hi-Z state with pull-up on
11: Setting prohibited
0
R/W Controls the pin state for DRAK1 in software
1
R/W standby mode.
00: Hi-Z state
01: Output
10: Hi-Z state with pull-up on
11: Setting prohibited
All 0
R
Reserved
These bits are always read as 0, and the write
value should always be 0.
0
R/W Controls a DMABRG reset.
0: Cancels DMABRG reset
1: Resets DMABRG
Note: For the BRGRST usage, refer to section
11.7.1, DMABRG Reset.
Rev. 1.0, 02/03, page 876 of 1294