SH7760 Datasheet, PDF (585/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
31 to 16 —
15 to 0 Channel n
counter
Note: n = 3 to 0
Initial Value R/W
—
R
All 0
R/W
Description
Reserved
These bits can only be read from. The write
value should always be 0.
Channel n Counter
A register for each channel indicates the
current value of the counters. This register
can be written to for setting the counter
values. Reading from these registers does not
affect the count value.
16.4 Operation
The timer consists of two sections of which the first is a 32-bit free-running timer for which the
clock can be set to operate between approximately 1 MHz and 30 kHz. The second section
consists of four 16-bit counters with the ability to count up and the ability to count down. This
counting is controlled through edge detection on the input pins. The timer and counters can be
used as counters which count based on inputs or can operate as timers with input capture/output
compare. They differ from the 32-bit timer of the FRT in that they are reset to H'0000 when a
capture or compare occurs on that channel.
The timer/counter consists of four channels, each of which can be configured as a timer or a
counter. In timer mode, each of the four channels has two operating modes: input capture mode
and output compare mode.
16.4.1 Edge Detection
The timers and counters are based on edge detection on the input pins. An active edge can be
programmed to be a rising edge, falling edge, or both edges. In addition, the edge detection logic
can operate in rotary switch mode where the combination of two inputs indicates whether the
switch has been turned right or left. This switch indicates increment or decrement of the updown-
counter. Edge detection operating on two inputs functions as a pair. The outputs can either work
independently for the timers or the up-counters or can work as pairs to indicate up and down to the
updown-counters.
In order for an edge to be detected, the pulse must last for at least two cycles of the clock divided
from the source clock for that channel, as shown in figure 16.2.
Rev. 1.0, 02/03, page 535 of 1294