SH7760 Datasheet, PDF (392/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

The MPX interface timing is shown below.
When the MPX interface is used for areas 1 to 6, a bus size of 32 bits should be specified by
BCR2.
In wait control, waits can be specified by WCR2 and waits can be inserted by the RDY pin.
In a read, one wait cycle is automatically inserted after address output, even if WCR2 is cleared to
0.
CKIO
RD/FRAME
D31−D0
CSn
RD/WR
Tm1
Tmd1w
Tmd1
A
D0
RDY
BS
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level)
= 0 for the DMAC.
Figure 10.44 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait)
Rev. 1.0, 02/03, page 342 of 1294