SH7760 Datasheet, PDF (40/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Section 33 Electrical Characteristics
Figure 33.1 EXTAL Clock Input Timing .................................................................................1200
Figure 33.2 CKIO Clock Output Timing (1) ............................................................................1201
Figure 33.3 CKIO Clock Output Timing (2) ............................................................................1201
Figure 33.4 DCK Clock Output Timing (1)..............................................................................1201
Figure 33.5 DCK Clock Output Timing (2)..............................................................................1201
Figure 33.6 Power-On Oscillation Settling Time (1)................................................................1202
Figure 33.7 Standby Return Oscillation Settling Time (Return by RESET or MRESET) (1)..1202
Figure 33.8 Power-On Oscillation Settling Time (2)................................................................1203
Figure 33.9 Standby Return Oscillation Settling Time (Return by RESET or MRESET) (2)..1203
Figure 33.10 Standby Return Oscillation Settling Time (Return by NMI)...............................1204
Figure 33.11 Standby Return Oscillation Settling Time (Return by IRL3 to IRL0).................1204
Figure 33.12 PLL Synchronization Settling Time in Case of RESET, MRESET or NMI
Interrupt ...............................................................................................................1204
Figure 33.13 PLL Synchronization Settling Time in Case of IRL Interrupt.............................1205
Figure 33.14 MD pins Setup/Hold Timing ...............................................................................1205
Figure 33.15 Control Signal Timing .........................................................................................1206
Figure 33.16 Pin Drive Timing for Standby Mode ...................................................................1207
Figure 33.17 SRAM Bus Cycle: Basic Bus Cycle (No Wait)...................................................1209
Figure 33.18 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait)....................................1210
Figure 33.19 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait)..1211
Figure 33.20 SRAM Bus Cycle: Basic Bus Cycle
(No Wait, Address Setup/Hold Time Insertion, AnS=1, AnH=1) .......................1212
Figure 33.21 Burst ROM Bus Cycle (No Wait)........................................................................1213
Figure 33.22 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait ;
2nd/3rd/4th Data: One Internal Wait)..................................................................1214
Figure 33.23 Burst ROM Bus Cycle
(No Wait, Address Setup/Hold Time Insertion, AnS=1, AnH=1) .......................1215
Figure 33.24 Burst ROM Bus Cycle (One Internal Wait + One External Wait) ......................1216
Figure 33.25 Synchronous DRAN Auto-Precharge Read Bus Cycle: Single
(RCD[1:0]=01, CAS Latency=3, TPC[2:0]=011) ...............................................1217
Figure 33.26 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst
(RCD[1:0]=01, CAS Latency=3, TPC[2:0]=011) ...............................................1218
Figure 33.27 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands,
Burst (RCD[1:0]=01, CAS Latency=3) ...............................................................1219
Figure 33.28 Synchronous DRAM Normal Read Bus Cycle:
PRE + ACT + READ Commands, Burst
(RCD[1:0]=01, TPC[2:0]=001, CAS Latency=3) ...............................................1220
Figure 33.29 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst
(CAS Latency=3).................................................................................................1221
Figure 33.30 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single
(RCD[1:0]=01, TPC[2:0]=001, TRWL[2:0]=010) ..............................................1222
Rev. 1.0, 02/03, page xxxviii of xlviii