SH7760 Datasheet, PDF (52/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

1.1
Item
LSI
CPU
Features
Features
• Operating frequency: 200 MHz
• Performance: 360MIPS, 1.4 GFLOPS
• Voltage: 1.5 V (internal), 3.3 V (I/O)
• Superscalar architecture: Parallel execution of two instructions
• Packages: 256-pin BGA (Size: 21 × 21 mm, pin pitch: 1.0 mm)
• External buses:
 Separate 26-bit address and 32-bit data buses
 External bus frequency: 67MHz
• Choice of MFI mode or LCD mode:
 MFI mode: 8-/16-bit parallel interface
(supports 68-/80-family interface)
 LCD mode: LCD controller/data output
• Original Hitachi SuperH architecture
• 32-bit internal data bus
• General register file:
 Sixteen 32-bit general registers (and eight 32-bit shadow registers)
 Seven 32-bit control registers
 Four 32-bit system registers
• RISC-type instruction set (upward-compatible with SuperH Series)
 Fixed 16-bit instruction length for improved code efficiency
 Load-store architecture
 Delayed branch instructions
 Conditional execution
 C-based instruction set
• Superscalar architecture (providing simultaneous execution of two
instructions) including FPU
• Instruction execution time: Maximum 2 instructions/cycle
• Virtual address space: 4 Gbytes (448-Mbyte external memory space)
• Space identifier ASIDs: 8 bits, 256 virtual address spaces
• On-chip multiplier
• 5-stage pipeline
Rev. 1.0, 02/03, page 2 of 1294