SH7760 Datasheet, PDF (1150/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
31 to 0
Bit Name
BDMB31 to
BDMB0
Note: n = 31 to 0
Initial Value R/W
—
R/W
Description
Break Data Mask B
These bits specify whether the corresponding bit of
the channel B break data Bn set in BDRB is to be
masked.
0: Channel B break data Bn is included in break
conditions
1: Channel B break data Bn is masked, and not
included in break conditions
31.2.9 Break Control Register (BRCR)
BRCR is a 16-bit readable/writable register that specifies (1) whether channels A and B are to be
used as two independent channels or in a sequential condition, (2) whether the break is to be
effected before or after instruction execution, (3) whether the BDRB register is to be included in
the channel B break conditions, and (4) whether the user break debug function is to be used.
BRCR also contains condition match flags. The CMFA, CMFB, and UBDE bits in BRCR are
initialized to 0 by a power-on reset, but retain their value in standby mode. The PCBA, DBEB,
PCBB, and SEQ bits are undefined after a power-on reset or manual reset, so these bits should be
initialized by software as necessary.
Bit: 15 14 13 12 11 10 9
CMFA CMFB -
-
- PCBA -
Initial value: 0
0
0
0
0
-
0
R/W: R/W R/W R
R
R R/W R
8
7
6
5
- DBEB PCBB -
0
-
-
0
R R/W R/W R
4
3
2
- SEQ -
0
-
0
R R/W R
1
0
- UBDE
0
0
R R/W
Bit
Bit Name Initial Value R/W Description
15
CMFA
0
R/W Condition Match Flag A
Set to 1 when a break condition set for channel A
is satisfied. This flag is not cleared to 0. To confirm
that the flag is set again after once being set, it
should be cleared with a write.
0: Channel A break condition does not matched
1: Channel A break condition has matched
14
CMFB
0
R/W Condition Match Flag B
Set to 1 when a break condition set for channel B
is satisfied. This flag is not cleared to 0. To confirm
that the flag is set again after once being set, it
should be cleared with a write.
0: Channel B break condition is not matched
1: Channel B break condition match has occurred
Rev. 1.0, 02/03, page 1100 of 1294