SH7760 Datasheet, PDF (877/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W
5
IDIV
0
R/W
4 to 0 CLKC
All 0
R/W
4 to 0
Description
Initial Clock Division Ratio
0: The peripheral clock is divided by a factor of 4
initially to create an intermediate frequency,
which is further divided to create the serial bit
clock when master mode.
1: The peripheral clock is divided by a factor of 32
initially to create an intermediate frequency,
which is further divided to create the serial bit
clock when master mode.
Clock Division Count
These bits determine the number of intermediate
frequency cycles long both the high and low
periods of the serial bit clock.
00000: 1 intermediate frequency cycle.
Serial bit clock frequency = Intermediate
frequency / 2.
00001: 2 Intermediate frequency cycles.
Serial bit clock frequency = Intermediate
frequency / 4.
00010: 3 intermediate frequency cycles.
:
11111:
Serial bit clock frequency = Intermediate
frequency / 6.
32 intermediate frequency cycles.
Serial bit clock frequency = Intermediate
frequency / 64.
The serial bit clock frequency can be computed using the following formula:
Pck
Serial bit clock frequency =
(Initial clock division × (Clock division count + 1) × 2
When the HSPI is configured as a slave, the IDIV and CLKC bits are ignored and the HSPI
synchronizes to the externally supplied serial bit clock. The maximum value of the external serial
bit clock that the module can operate with is peripheral clock frequency / 8.
If any of the FBS, CLKP, IDIV or CLKC bit values are changed, then the HSPI will undergo the
HSPI software reset.
Rev. 1.0, 02/03, page 827 of 1294