SH7760 Datasheet, PDF (1305/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 33.23 AC Characteristics of 68 Series Bus
Item
Symbol Min.
Max.
Unit Figure
Read bus cycle time
t_MFICYCR
4× t_Pcyc+10
—
ns
33.72
Write bus cycle time
t_MFICYCW
3× t_Pcyc+10
—
ns
Address setup time (MFI-RS)
t
0
MFIAS
—
ns
(MFI-RW/RD) t
10
—
ns
MFIAS
Address hold time (MFI-RS)
t_MFIAH
0
—
ns
(MFI-RW/RD) t_MFIAH
10
—
ns
Enable high width (Read)
t_MFIWRH
2.5× t_Pcyc
—
ns
Enable low width (Write)
t
MFIWEH
1.5×
t
Pcyc
—
ns
Enable low width
t
MFIWEL
2.0×
t +5
Pcyc
—
ns
Read data delay time
t
—
MFIRDD
2×
t +10
Pcyc
ns
Read data hold time
t_MFIRDH
0
—
ns
Write data setup time
t_MFIWDS
t_Pcyc+10
—
ns
Write data hold time
t
10
—
ns
MFIWDH
Notes: 1. t_Pcyc : one Pck cycle time
2. t_MFIWEH is the time where the low level of MFI-CS and the high level of MFI-E/WR are
overlapped.
MFI-RW/RD
MFI-RS
t_MFICYCR
t_MFIWRH
t_MFICYCW
t_MFIWEH
MFI-CS
MFI-E/WR
MFI-D15-
MFI-D0
t_MFIAS
t_MFIAH
t_MFIAS
t_MFIRDD
t_MFIWEL
t_MFIRDH
Read data
t_MFIAH
t_MFIWDS t_MFIWDH
Write data
Figure 33.72 AC Characteristics of 68 Series Bus
Rev. 1.0, 02/03, page 1255 of 1294