SH7760 Datasheet, PDF (984/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit Name Value R/W
3 CRPI 0
R/W
2 CMDI 0
R/W
1 DBSYI 0
R/W
0
0
R
Description
Command Response Receive End Interrupt
0: No interrupt
[Clearing condition]
Write 0 after reading CRPI = 1.
1: Interrupt requested
[Setting condition]
When command response reception ends while
CRPIE = 1.
Command Transmit End Interrupt
0: No interrupt
[Clearing condition]
Write 0 after reading CMDI = 1.
1: Interrupt requested
[Setting condition]
When command transmission ends while
CMDIE = 1. (When the CWRE bit in CSTR is
cleared.)
Data Busy End Interrupt
0: No interrupt
[Clearing condition]
Write 0 after reading DBSYI = 1.
1: Interrupt requested
[Setting condition]
When data busy state is canceled while
DBSYIE = 1. (When the DTBUSY bit in CSTR is
cleared.)
Reserved
This bit is always read as 0. The write value
should always be 0.
Interrupt
output
MMCI1
MMCI1
MMCI1

Rev. 1.0, 02/03, page 934 of 1294