SH7760 Datasheet, PDF (708/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
31 to 3 
Initial Value R/W
All 0
R
2
TEND
0
R/W
1
RDF
0
R/W
Description
Reserved.
These bits are always read as 0, and the write
value should always be 0.
Transmit End
Indicates the end of transmission with no valid
data in ICTXD when the last bit of the character is
transmitted.
0: Indicates transmission in progress
[Clear conditions]
• Power-on reset, or manual reset
• When transmit data is written to ICTXD and 0
to the TEND flag.
1: Indicates transmission end
[Set conditions]
• When there is no transmit data in ICTXD when
the last bit of the 1-byte character is
transmitted.
Receive FIFO Data Full
Indicates that the receive data is transferred from
the shift register to ICRXD, and the byte count in
ICRXD reaches the receive trigger byte count set
in the RTRG3 to RTRG0 bits in ICFCR.
When RDF is set to 1, the receive operation
stops. Reading the receive data from ICRXD and
clearing RDF to 0 will resume a receive operation.
0: Indicates that the byte count in ICRXD is
smaller than the receive trigger byte count.
[Clear condition]
• Power-on reset, or manual reset
• Reading from ICRXD has made the byte count
in ICRXD smaller than the receive trigger byte
count, and 0 is written to RDF.
1: Indicates that the byte count in ICRXD reaches
the receive trigger byte count.
[Set condition]
• The byte count in ICRXD exceeds the receive
trigger byte count.*¹
Rev. 1.0, 02/03, page 658 of 1294