SH7760 Datasheet, PDF (832/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
4,3

All 0
R
Reserved
The write value should always be 0. The read
value is not guaranteed.
2
MCR2
0
R/W Message Transmission Priority
Selects the order of transmission for pending
transmit data. When this bit is set, pending
transmit data are sent in order of the bit position in
CANTXPR. The order of transmission starts from
Mailbox 31 as the highest priority, and then down
to Mailbox 1 (if those mailboxes are configured for
transmission).
If this bit is cleared, all transmit messages are
queued with respect to their priority (by running
internal arbitration). The highest priority message
has the Arbitration Field with the lowest digital
value and is transmitted first. The internal
arbitration includes the RTR bit and the IDE bit.
0: Transmission order is determined by the
message identifier priority.
1: Transmission order is determined by the
Mailbox number priority (Mailbox 31 Æ Mailbox
1).
1
MCR1
0
R/W Halt Request
When this bit is set, the CAN controller completes
its current operation and then to be cut off the
CAN bus. HCAN2 remains in this Halt Mode until
this bit is cleared. During the Halt Mode, the CAN
Interface does not join the CAN bus activity or
does not store messages nor transmit messages.
All the registers and Mailbox contents retain.
HCAN2 will complete the current operation if it is
a transmitter or a receiver, and then enter the Halt
Mode. If the CAN bus is in idle or intermission
state, HCAN2 will enter the Halt Mode
immediately. Entering the Halt Mode is notified by
IRR0 and GSR4.
In the Halt Mode, HCAN2 configuration can be
modified as it does not join the bus activity. This
bit has be cleared by writing a 0 to re-join the
CAN bus. After this bit is cleared, the CAN
Interface waits until it detects 11 recessive bits,
and then joins the CAN bus.
0: Normal operating mode
1: Halt Mode transition request.
Rev. 1.0, 02/03, page 782 of 1294