SH7760 Datasheet, PDF (452/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Specify this register value as a shared memory address for a DMA transfer from synchronous
DRAM to the shared memory, and as a synchronous DRAM address for a transfer from the shared
memory to synchronous DRAM. In the case of a transfer from synchronous DRAM to the shared
memory, the address should be within the transfer destination, that is the shared memory area
(H’FE34 1000 to H’FE34 2FFC). When an address outside of this area is specified, the DMAC
detects a USB address error and terminates the USB DMA transfer.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
11.3.19 DMA USB R/W Size Register (DMAURWSZ)
DMAURWSZ is a 32-bit readable/writable register that specifies the transfer direction and data
size. During USB DMA transfer, the register value can be read but cannot be modified.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- RW
Initial value: 0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
RR
R
R
R
R
R
R
R
R R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
- SZ12 SZ11 SZ10 SZ9 SZ8 SZ7 SZ6 SZ5 SZ4 SZ3 SZ2 SZ1 SZ0
Initial value: 0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 17 
16
RW
15 to 13 
Initial Value R/W
All 0
R
0
R/W
All 0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Transfer Direction
0: Specifies a DMA transfer from synchronous
DRAM to the shared memory
1: Specifies a DMA transfer from the shared
memory to synchronous DRAM
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.0, 02/03, page 402 of 1294