SH7760 Datasheet, PDF (861/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

CANIMR can prevent the generation of the interrupt signal. When Bit11 of CANTCR is set to 1, a
compare match with CANTCMR will clear the timer to 0 (Timer Clear/ Set function).
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR
15
14
13 12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value: ₀
0
00
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit
Bit Name
Initial Value R/W Description
15 to 0 TCMR[15:0] 0
R/W* Indicates the value of Free Running Timer.
Note: * This register is cleared by the Compare Match condition.
Rev. 1.0, 02/03, page 811 of 1294