SH7760 Datasheet, PDF (571/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

15.6 Usage Notes
15.6.1 Register Writes
When writing to a TMU register, timer count operation must be stopped by clearing the start bit
(STR2 to STR0) for the relevant channel in TSTR.
Note that TSTR can be written to, and the UNF and ICPF bits in TCR can be cleared while the
count is in progress. When the flags (UNF and ICPF) are cleared while the count is in progress,
make sure not to change the values of bits other than those being cleared.
15.6.2 Reading from TCNT
Reading from TCNT is performed synchronously with the timer count operation. Note that when
the timer count operation is performed simultaneously with reading from a register, the
synchronous processing causes the TCNT value before the count-down operation to be read as the
TCNT value.
15.6.3 External Clock Frequency
Ensure that the external clock (TCLK) frequency for each channel does not exceed Pck/4.
Rev. 1.0, 02/03, page 521 of 1294