SH7760 Datasheet, PDF (857/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
15 to 0 MBIMR1[15:0]
Initial Value R/W
All 1
R/W
Description
Enable or disable interrupt requests from
individual Mailboxes 31 to 16 respectively.
0: Interrupt requests from IRR1/IRR2/IRR8/
IRR9 enabled.
1: Interrupt requests from IRR1/IRR2/IRR8/
IRR9 disabled.
• CANMBIMR0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0
_15
_14
_13
_12
_11
_10
_9
_8
_7
_6
_5
_4
_3
_2
_1
_0
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
Initial Value R/W
15 to 0 MBIMR0[15:0] All 1
R/W
Description
Enable or disable interrupt requests from
individual Mailboxes 15 to 0 respectively.
0: Interrupt requests from IRR1/IRR2/IRR8/
IRR9 enabled.
1: Interrupt requests from IRR1/IRR2/IRR8/
IRR9 disabled.
22.5.14 Unread Message Status Registers 1 and 0 (CANUMSR1, CANUMSR0)
The CANUMSR are two 16-bit read/write registers and record any receive mailboxes that have
been emptied prior to a new message received. If the host CPU has not cleared the corresponding
bit in CANRXPR or CANRFPR when a new message for that mailbox is received, the
corresponding CANUMSR bit is set to 1. This bit may be cleared by writing a 1 to the
corresponding bit location in the CANUMSR. Writing a 0 has no effect.
If a mailbox is configured as a transmit box, the corresponding CANUMSR bit will not be set.
• CANUMSR1
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1
_15 _14 _13 _12 _11 _10
_9
_8
_7
_6
_5
_4
_3
_2
_1
_0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 807 of 1294