SH7760 Datasheet, PDF (39/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 28.2 TAP Controller State Transitions ..........................................................................1009
Figure 28.3 H-UDI Reset..........................................................................................................1010
Section 29 A/D Converter (ADC)
Figure 29.1 A/D Converter Block Diagram..............................................................................1014
Figure 29.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ..........1022
Figure 29.3 Example of A/D Converter Operation
(Multi Mode, Three Channels AN0 to AN2 Selected) .........................................1024
Figure 29.4 Example of A/D Converter Operation
(Scan Mode, Three Channels AN0 to AN2 Selected) ...........................................1026
Figure 29.5 Timing for Data Write when Four Channels are Selected in Multi Mode.............1027
Figure 29.6 External Trigger Input Timing ..............................................................................1029
Figure 29.7 Definitions of A/D Conversion Accuracy .............................................................1031
Figure 29.8 Example of Analog Input Pin Protection Circuit...................................................1032
Figure 29.9 Analog Input Pin Equivalent Circuit .....................................................................1032
Section 30 LCD Controller (LCDC)
Figure 30.1 LCDC Block Diagram...........................................................................................1036
Figure 30.2 Valid Display and the Retrace Period....................................................................1063
Figure 30.3 Color-Palette Data Format.....................................................................................1065
Figure 30.4 Power-Supply Control Sequence and States of the LCD Module .........................1070
Figure 30.5 Power-Supply Control Sequence and States of the LCD Module .........................1070
Figure 30.6 Power-Supply Control Sequence and States of the LCD Module .........................1071
Figure 30.7 Power-Supply Control Sequence and States of the LCD Module .........................1071
Figure 30.8 Clock and LCD Data Signal Example ...................................................................1077
Figure 30.9 Clock and LCD Data Signal Example ...................................................................1077
Figure 30.10 Clock and LCD Data Signal Example .................................................................1078
Figure 30.11 Clock and LCD Data Signal Example .................................................................1078
Figure 30.12 Clock and LCD Data Signal Example .................................................................1079
Figure 30.13 Clock and LCD Data Signal Example .................................................................1080
Figure 30.14 Clock and LCD Data Signal Example .................................................................1080
Figure 30.15 Clock and LCD Data Signal Example .................................................................1081
Figure 30.16 Clock and LCD Data Signal Example .................................................................1081
Figure 30.17 Clock and LCD Data Signal Example .................................................................1082
Figure 30.18 Clock and LCD Data Signal Example .................................................................1083
Figure 30.19 Clock and LCD Data Signal Example .................................................................1084
Figure 30.20 Clock and LCD Data Signal Example .................................................................1085
Figure 30.21 Clock and LCD Data Signal Example .................................................................1086
Figure 30.22 Clock and LCD Data Signal Example .................................................................1087
Section 31 User Break Controller (UBC)
Figure 31.1 Block Diagram of UBC .........................................................................................1090
Figure 31.2 User Break Debug Support Function Flowchart....................................................1110
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