SH7760 Datasheet, PDF (662/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
5 ORER
4 ERS
Initial
Value R/W Description
0
R/W Overrun Error
Indicates that an overrun error resulting in abnormal
termination has occurred during reception..
0: Indicates that reception is in progress, or that reception
was completed normally*¹
[Clearing Conditions]
• On reset
• When 0 is written to ORER
1: Indicates that an overrun error occurred during reception*²
[Setting Condition]*³
• When the next serial reception is completed in the RDRF
= 1 state.
Notes: *1. Clearing the RE bit in SISCR to 0 will retain the
previous state without affecting the ORER flag.
*2. SIRDR loses the data received before the overrun
error but retains the data received at the time the
overrun error occurred. Furthermore, if ORER is
set to 1, then subsequent serial reception cannot
continue.
*3. Writing 1 will retain the original value.
0
R/W Error Signal Status
This flag indicates the status of error signals returned from
the receiver during transmission. In the T = 1 mode, this bit
is not set.
0: Indicates that an error signal indicating detection of a
parity error was not sent from the receiver.
[Clearing Conditions]
• On reset
• When 0 is written to ERS
1: Indicates that an error signal indicating detection of a
parity error was sent from the receiver.
[Setting Condition]
• When an error signal is sampled.
Note: Clearing the TE bit in SISCR to 0 will retain the
previous state without affecting the ERS flag.
Rev. 1.0,02/03, page 612 of 1294