SH7760 Datasheet, PDF (972/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 26.5 Correspondence between Command Response Byte Number and RSPR
RSPR registers
RSPR0
RSPR1
RSPR2
RSPR3
RSPR4
RSPR5
RSPR6
RSPR7
RSPR8
RSPR9
RSPR10
RSPR11
RSPR12
RSPR13
RSPR14
RSPR15
RSPR16
MMC Mode Response
6 bytes (R1, R1b, R3, R4, R5)











1st byte
2nd byte
3rd byte
4th byte
5th byte
6th byte
17 bytes (R2)
1st byte
2nd byte
3rd byte
4th byte
5th byte
6th byte
7th byte
8th byte
9th byte
10th byte
11th byte
12th byte
13th byte
14th byte
15th byte
16th byte
17th byte
RSPR0 to RSPR16 are simple shift registers. A command response that has been shifted in is not
automatically cleared, and it is continuously shifted until it is shifted out from bit 7 in RSPR0. To
clear unnecessary bytes to H'00, write an arbitrary value to each RSPR.
Clearing an RSPR is completed two transfer clock cycles after an arbitrary value is written to the
RSPR.
• RSPR0 to RSPR16
Bit: 7
6
5
4
3
2
1
0
RSPR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 922 of 1294