SH7760 Datasheet, PDF (581/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W
27
IOE3
0
R/W
26
IOE2
0
R/W
25
IOE1
0
R/W
24
IOE0
0
R/W
23
ICE3
0
R/W
22
ICE2
0
R/W
21
ICE1
0
R/W
20
ICE0
0
R/W
19
IEE3
0
R/W
18
IEE2
0
R/W
17
IEE1
0
R/W
16
IEE0
0
R/W
15, 14 CC3
All 0
R/W
13, 12 CC2
All 0
R/W
Description
Channel 3 to 0 Interrupt Overflow Enable
These bits enable an interrupt to be generated
when the relevant IOn bit is set in the IRQ status
register.
0: Interrupt generation disabled
1: Interrupt generation enabled
Channel 3 to 0 Interrupt Compare Enable
These bits enable an interrupt to be generated
when the relevant ICn bit is set in the IRQ status
register.
0: Interrupt generation disabled
1: Interrupt generation enabled
Channel 3 to 0 Interrupt Edge Enable
These bits enable an interrupt to be generated
when the relevant IEn bit is set in the IRQ status
register.
0: Interrupt generation disabled
1: Interrupt generation enabled
When a channel is in outup compare mode, the
corresponding IEEn has to be set to 0.
Timer Clock Control Channel 3
These bits specify the clock input for the 16-bit
timer/counter in channel 3.*¹
00: Clock for timer 3 is 1/32 of source clock
01: Clock for timer 3 is 1/128 of source clock
10: Clock for timer 3 is 1/512 of source clock
11: Clock for timer 3 is 1/1024 of source clock
Set the same value as the CC0 bit when using 16-
bit input capture mode.
Timer Clock Control Channel 2
These bits specify the clock input for the 16-bit
timer/counter in channel 2.*¹
00: Clock for timer 2 is 1/32 of source clock
01: Clock for timer 2 is 1/128 of source clock
10: Clock for timer 2 is 1/512 of source clock
11: Clock for timer 2 is 1/1024 of source clock
Set the same value as the CC0 bit when using 16-
bit input capture mode.
Rev. 1.0, 02/03, page 531 of 1294