SH7760 Datasheet, PDF (491/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

11.4.6 Ending DMA Transfer
The conditions for ending DMA transfer are different for ending on individual channels and for
ending on all channels simultaneously. Following are the procedures for ending transfer, except
for ending transfer when the DMATCR value reaches 0.
1. Cycle steal mode (external request, on-chip peripheral module request, auto-request)
When transfer end conditions are met, the DMAC waits until all ongoing DMA transfers
requested before transfer end conditions are complete, and then stops the operation. In cycle
steal mode, the operation is the same for both edge and level transfer request detection.
2. Burst mode, edge detection (external request, DMABRG request, on-chip peripheral module
request, auto-request)
It generates the same delay between the time transfer end conditions are met and the time the
DMAC stops the operation as in cycle steal mode. In burst mode with edge detection, only the
first transfer request activates the DMAC, but the timing of stop request (DE = 0 in CHCR,
DME = 0 in DMAOR) sampling is the same as the transfer request sampling timing shown in
Burst Mode, Single Address Mode, Edge Detection and Suspension of DMA Transfer with
DREQ Level Detection under Operation in section 11.4.5 (3). Therefore, a transfer request is
regarded as having been issued until a stop request is detected, and the corresponding
processing is executed before the DMAC stops.
3. Burst mode, level detection (external request)
It generates the same delay between the time transfer end conditions are met and the time the
DMAC stops the operation as in cycle steal mode. As in the case of burst mode with edge
detection, the timing of stop request (DE = 0 in CHCR, DME = 0 in DMAOR) sampling is the
same as the transfer request sampling timing shown in Burst Mode, Single Address Mode,
Edge Detection and Suspension of DMA Transfer in Case of DREQ Level Detection under
Operation in section 11.4.5 (3). Therefore, a transfer request is regarded as having been issued
until a stop request is detected, and the corresponding processing is executed before the
DMAC stops.
4. Bus timing for transfer suspension
The DMAC suspends the operation after processing for one bus cycle unit is complete. In dual
address mode transfer, the DMAC executes write cycle processing even if a transfer end
condition is satisfied during the read cycle. It suspends the operation after completing the
transfers mentioned above in 1, 2, and 3.
Rev. 1.0, 02/03, page 441 of 1294