SH7760 Datasheet, PDF (561/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

15.3 Register Descriptions
The TMU has the following registers. For details on the addresses of these registers and the state
of registers in each operating mode, see section 32, List of Registers.
Table 15.2 Register Configuration (1)
Ch. Register Name
Common Timer start register
0
Timer constant register 0
Timer counter 0
Timer control register 0
1
Timer constant register 1
Timer counter 1
Timer control register 1
2
Timer constant register 2
Timer counter 2
Timer control register 2
Input capture register 2
Abbrev. R/W
TSTR R/W
TCOR0 R/W
TCNT0 R/W
TCR0 R/W
TCOR1 R/W
TCNT1 R/W
TCR1 R/W
TCOR2 R/W
TCNT2 R/W
TCR2 R/W
TCPR2 R
P4 Address
H’FFD8 0004
H’FFD8 0008
H’FFD8 000C
H’FFD8 0010
H’FFD8 0014
H’FFD8 0018
H’FFD8 001C
H’FFD8 0020
H’FFD8 0024
H’FFD8 0028
H’FFD8 002C
Sync
Area 7 Address Size Clock
H’1FD8 0004 8
Pck
H’1FD8 0008 32 Pck
H’1FD8 000C 32 Pck
H’1FD8 0010 16 Pck
H’1FD8 0014 32 Pck
H’1FD8 0018 32 Pck
H’1FD8 001C 16 Pck
H’1FD8 0020 32 Pck
H’1FD8 0024 32 Pck
H’1FD8 0028 16 Pck
H’1FD8 002C 32 Pck
Rev. 1.0, 02/03, page 511 of 1294