SH7760 Datasheet, PDF (1142/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 31.1 Register Configuration (2)
Register Name
Abbrev.
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
Manual Reset
by RESET Sleep
Pin/WDT/ by Sleep
Multiple
Instruction/
Exception Deep Sleep
Standby
by Software/
by Hardware Each Module
Break address register A
BARA
Undefined Retained Retained
*
Retained
Break ASID register A
BASRA Undefined Retained Retained
Retained
Break address mask register A BAMRA Undefined Retained Retained
Retained
Break bus cycle register A
BBRA
H′0000
Retained Retained
Retained
Break address register B
BARB
Undefined Retained Retained
Retained
Break ASID register B
BASRB Undefined Retained Retained
Retained
Break address mask register B BAMRB Undefined Retained Retained
Retained
Break bus cycle register B
BBRB
H′0000
Retained Retained
Retained
Break data register B
BDRB
Undefined Retained Retained
Retained
Break data mask register B BDMRB Undefined Retained Retained
Retained
Break control register
BRCR
H′0000*¹ Retained Retained
Retained
Note: * After exiting hardware standby mode, this LSI enters the power-on reset state caused
by the RESET pin.
*1 This value includes an undefined bit value. Refer to the register description.
The access size must be the same as the control register size. If the access size is different from the
register size, no data will be written to the register and an undefined value will be read.
UBC control register contents cannot be transferred to a floating-point register using a floating-
point memory data transfer instruction. When a UBC control register is updated, use either of the
following methods to make the updated value valid:
1. Execute an RTE instruction after the memory store instruction that updated the register. The
updated value will be valid from the RTE instruction destination onward.
2. Execute instructions requiring 5 states for execution after the memory store instruction that
updated the register. This LSI executes two instructions in parallel and a minimum of 0.5 states
are required for execution of one instruction, 11 instructions must be inserted. The updated
value will be valid from the 6th state onward.
Rev. 1.0, 02/03, page 1092 of 1294