SH7760 Datasheet, PDF (190/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Effective address
31
25
13 12 11 10
54 2 0
IIX
22
[12]
Entry
selection
Address array
8
(way 0, way1) 3
0
Tag
V
[11:5]
Longword (LW)
selection
Data array (way 0, way 1)
LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
LRU
MMU
19
255 19 bits 1 bit
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 1 bit
Compare Compare
way 0 way 1
Read data
Hit signal
Figure 7.2 Configuration of Instruction Cache
• Tag
Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is
not initialized by a power-on or manual reset.
• V bit (validity bit)
Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is
valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
• U bit (dirty bit)
The U bit is set to 1 if data is written to the cache line while the cache is being used in copy-
back mode. That is, the U bit indicates a mismatch between the data in the cache line and the
data in external memory. The U bit is never set to 1 while the cache is being used in write-
through mode, unless it is modified by accessing the memory-mapped cache (see section 7.5,
Memory-Mapped Cache Configuration (Cache Direct Mapping Mode)). The U bit is initialized
to 0 by a power-on reset, but retains its value in a manual reset.
Rev. 1.0, 02/03, page 140 of 1294