SH7760 Datasheet, PDF (575/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 16.2 Register Configuration (2)
Ch.
Register Name
Abbrev.
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
Manual Reset
Standby
by RESET Sleep
by
Pin/WDT/ by Sleep
Software/E
Multiple
Instruction/ by
ach
Exception Deep Sleep Hardware Module
Common Configuration register
CMTCFG H’0000 0000 H’0000 0000 Retained
* Retained
Free-running timer
CMTFRT H’0000 0000 H’0000 0000 Retained
Retained
Control register
CMTCTL H’0000 0000 H’0000 0000 Retained
Retained
IRQ status register
CMTIRQS H’0000 0000 H’0000 0000 Retained
Retained
0
Channel 0 time register
CMTCH0T H’0000 0000 H’0000 0000 Retained
Retained
Channel 0 stop time register CMTCH0ST H’0000 0000 H’0000 0000 Retained
Retained
Channel 0 timer/counter
CMTCH0C H’0000 0000 H’0000 0000 Retained
Retained
1
Channel 1 time register
CMTCH1T H’0000 0000 H’0000 0000 Retained
Retained
Channel 1 stop time register CMTCH1ST H’0000 0000 H’0000 0000 Retained
Retained
Channel 1 timer/counter
CMTCH1C H’0000 0000 H’0000 0000 Retained
Retained
2
Channel 2 time register
CMTCH2T H’0000 0000 H’0000 0000 Retained
Retained
Channel 2 stop time register CMTCH2ST H’0000 0000 H’0000 0000 Retained
Retained
Channel 2 timer/counter
CMTCH2C H’0000 0000 H’0000 0000 Retained
Retained
3
Channel 3 time register
CMTCH3T H’0000 0000 H’0000 0000 Retained
Retained
Channel 3 stop time register CMTCH3ST H’0000 0000 H’0000 0000 Retained
Retained
Channel 3 timer/counter
CMTCH3C H’0000 0000 H’0000 0000 Retained
Retained
Notes: * After exiting hardware standby mode, this LSI enters the power-on reset state caused by
the RESET pin.
Rev. 1.0, 02/03, page 525 of 1294