SH7760 Datasheet, PDF (978/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
15 to 0
Bit
Name
DTOUTR
Initial
Value
All 1
R/W Description
R/W Data Timeout Time/10,000
Data timeout time: Peripheral clock cycle x DTOUTR
setting value x 10,000.
26.3.11 Card Status Register (CSTR)
CSTR indicates the MMCIF status during command sequence execution.
Bit: 7
6
5
4
3
2
1
0
BUSY
FIFO_
FULL
FIFO_
EMPTY
CWRE
DTBUSY
DTBUSY
_TU
-
REQ
Initial value: 0
0
0
0
0
-
0
0
R/W: R
RR
RR
R
R
R
Bit
Bit Name
7 BUSY
6 FIFO_
FULL
5 FIFO_
EMPTY
Initial
Value R/W Description
0
R
Command Busy
Indicates command execution status. When the CMDOFF
bit in OPCR is set to 1, this bit is cleared to 0 because the
MMCIF command sequence is aborted.
0: Idle state waiting for a command, or data busy state
1: Command sequence execution in progress
0
R
FIFO Full
This bit is set to 1 when the FIFO becomes full while data
is being received from the card, and cleared to 0 when
RD_CONTI is set to 1 or the command sequence is
completed.
Indicates whether the FIFO is empty or not.
0: The FIFO is empty.
1: The FIFO is full.
0
R
FIFO Empty
This bit is set to 1 when the FIFO becomes empty while
data is being sent to the card, and cleared to 0 when
DATA_EN is set to 1 or the command sequence is
completed.
Indicates whether the FIFO holds data or not.
0: The FIFO includes data.
1: The FIFO is empty.
Rev. 1.0, 02/03, page 928 of 1294