SH7760 Datasheet, PDF (1058/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

28.3.3 Interrupt Source Register (SDINT)
SDINT is a 16-bit register that can be read from/written to by the CPU. Specifying an H-UDI
interrupt command in SDIR via H-UDI pin (Update-IR) sets the INTREQ bit to 1. While SDIR
contains an H-UDI interrupt command, SDINT is connected between the TDI and TDO pins.
SDINT can be read as a 32-bit register; the upper 16 bits will be 0 and the lower 16 bits represent
the SDINT register.
The CPU can write 0 alone to the INTREQ bit. As long as this bit is set to 1, an interrupt request
will continue to be generated. Therefore, the INTREQ bit must be cleared to 0 during the interrupt
handler. The SDINT register is initialized when TRST is driven low or the TAP controller enters
the Test-Logic-Reset state.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- INTREQ
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Bit Bit Name Initial Value R/W Description
15 to 1 —
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
INTREQ 0
R/W Interrupt Request
Indicates whether or not an interrupt request by an H-
UDI interrupt command has occurred. Clearing this bit
to 0 by the CPU cancels an interrupt request. Writing 1
to this bit retains the previous value.
Rev. 1.0, 02/03, page 1008 of 1294