SH7760 Datasheet, PDF (162/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TTB
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TTB
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
6.2.5 TLB Exception Address Register (TEA)
TEA can be accessed in longwords from H'FF00 000C in the P4 area and from H'1F00 000C in
area 7. After an MMU exception or address error exception occurs, the virtual address at which the
exception occurred is set in TEA by hardware. The contents of this register can be changed by
software.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Virtual address at which MMU exception or address error occurred
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Virtual address at which MMU exception or address error occurred
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
6.2.6 MMU Control Register (MMUCR)
MMUCR can be accessed in longwords from H'FF00 0010 in the P4 area and from H'1F00 0010
in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR
rewriting should be performed by a program in the P1 or P2 area. After MMUCR is updated, an
instruction that performs data access to the P0, P3, U0, or store queue area should be located at
least four instructions after the MMUCR update instruction. Also, a branch instruction to the P0,
P3, or U0 area should be located at least eight instructions after the MMUCR update instruction.
MMUCR contents can be changed by software. However, the LRUI bits and URC bits may also
be updated by hardware.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LRUI
-
-
URB
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R
R R/W R/W R/W R/W R/W R/W R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
URC
SQMD SV -
-
-
-
-
TI
- _AT
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R/W R R/W
Rev. 1.0, 02/03, page 112 of 1294