SH7760 Datasheet, PDF (1090/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 30.3 I/O Clock Frequency and Clock Division Ratio
DCDR[4:0]
Clock Division
Ratio
50.000
I/O Clock Frequency (MHz)
60.000
66.000
00001
1/1
50.000
60.000
66.000
00010
1/2
25.000
30.000
33.000
00100
1/4
12.500
15.000
16.500
01000
1/8
6.250
7.500
8.250
10000
1/16
3.125
3.750
4.125
Note: Any setting other than above is handled as a clock division ratio of 1/1 (initial value).
30.3.2 LCDC Module Type Register (LDMTR)
LDMTR sets the control signals output from this LCDC and the polarity of the data signals,
according to the polarity of the signals for the LCD module connected to the LCDC.
Bit: 15 14 13 12 11 10 9
8
7
FLM CL1 DISP
POL POL POL ^DPOL
-
CL1 CL2
MCNT _{CNT CNT}
-
Initial value: 0
0
0
0
0
0
0
1
0
R/W: R/W R/W R/W R/W R R/W R/W R/W R
6
5
4
3
2
1
0
-
MIF MIF MIF MIF MIF MIF
TYP5 TYP4 TYP3 TYP2 TYP1 TYP0
0
0
0
1
0
0
1
R R/W R/W R/W R/W R/W R/W
Bit
Bit Name Initial Value R/W Description
15
FLMPOL 0
R/W FLM (Vertical Sync Signal) Polarity Select
Selects the polarity of the LCD_FLM (vertical sync
signal, first line marker) for the LCD module.
0: LCD_FLM pulse is high active
1: LCD_FLM pulse is low active
14
CL1POL 0
R/W CL1 (Horizontal Sync Signal) Polarity Select
Selects the polarity of the LCD_CL1 (horizontal sync
signal) for the LCD module.
0: LCD_CL1 pulse is high active
1: LCD_CL1 pulse is low active
13
DISPPOL 0
R/W DISP (Display Enable) Polarity Select
Selects the polarity of the LCD_M_DISP (display
enable) for the LCD module.
0: LCD_M_DISP is high active
1: LCD_M_DISP is low active
Rev. 1.0, 02/03, page 1040 of 1294