SH7760 Datasheet, PDF (430/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 11.3 External Request 2-Channel Mode (DMS[1:0] in DMAOR = 00)
Bit 11: Bit 10: Bit 9: Bit 8:
RS3 RS2 RS1 RS0 Description
0
0
0
0
External request*¹
Dual address mode
External address space → external address space
1
Setting prohibited
1
0
External request*¹
Single address mode
External address space → external device
1
External request*¹
Single address mode
External device → external address space
1
0
0
Auto-request (external address space → external address
space)
1
Auto-request (external address space → on-chip peripheral
module)
1
0
Auto-request (on-chip peripheral module → external address
space)
1
On-chip peripheral module request*²*³
External address space → on-chip peripheral module
1
0
0
0
Setting prohibited
1
Setting prohibited
1
0
Setting prohibited
1
Setting prohibited
1
0
0
TMU channel 2 (input capture interrupt)
External address space → external address space
1
TMU channel 2 (input capture interrupt)
External address space → on-chip peripheral module
1
0
TMU channel 2 (input capture interrupt)
On-chip peripheral module → external address space
1
On-chip peripheral module request*²*³
On-chip peripheral module → external address space
Notes: *1. External request specifications are valid only for channels 0 and 1. DREQ0 and DREQ1
correspond to channel 0 and channel 1, respectively.
*2. DMARSRA and DMARSRB values should be specified in addition to setting this bit.
*3. On-chip peripheral modules except for LCDC, HAC, SSI, USB, and TMU
Rev. 1.0, 02/03, page 380 of 1294